Roberto Medina

PhD in Computer Science, Real-Time and Embedded Systems · Paris, France

I am currently a Senior Research Engineer at Huawei Technologies.
My research interests are in the design, analysis and verification of Real-Time Embedded Systems.

Previously I was a research and development engineer at Expleo, working on in-house projects related to autonomous and adaptive driving.
Between 2019 and 2020, I worked as a post-doctoral researcher at the National Institute for Research in Computer Science and Control (Inria) in the Kopernic team.
I prepared my Ph.D. at Télécom ParisTech focusing on safety-critical data-driven applications incorporating the mixed-criticality model.


Senior Research Engineer

Huawei Technologies · Boulogne-Billancourt, France

I am currently developing new technologies for the next generation network equipment.
Particularly focusing on an execution environment delivering high performance in a secured fashion.

Domains of expertise:

  • OS design and programming
  • Virtualization
  • Real-Time systems
  • ARM64 architectures

From September 2020

Research and Development Engineer

Expleo Group · Montigny-le-Bretonneux, France

I supervised in-house research projects related to autonomous driving, in particular how SLAM and perception algorithms can be tuned, configured and integrated into a common embedded platform.
I was also in charge of improving resource and timing constraints on existing software used to control a R&D prototype for autonomous driving.

June 2020 - September 2020

Post-Doctoral Researcher

Inria · Paris, France

During my postdoc I was interested in probabilistic scheduling methods. I looked into integrating energy consumption constraints into probabilistic response time analysis for probabilistic real-time systems on unicore processors.
To achieve a realistic model I performed several experiments into real hardware platforms by varying processor and memory speeds.

February 2019 - May 2020

PhD Candidate/Researcher

Télécom ParisTech · Paris, France

My Ph.D. contributions were related to mixed-criticality scheduling for Directed Acyclic Graphs (DAGs). We designed a scheduling heuristic to compute scheduling tables for DAGs on multi-core architectures and we proposed a method to evaluate availability for this type of systems.
All these contributions have been gathered in an open-source framework called MC-DAG.

October 2015 - January 2019

Teaching Assistant

ESIEE - Télécom ParisTech · Paris, France

During my Ph.D. and postdoc I had the opportunity to be a lab assistant at ESIEE and Telecom ParisTech. Courses that I taughts were the following:

  • C programming and operating systems.
  • Real-time scheduling.
  • Modelisation, code generation and verification (using AADL).
  • Embedded Linux (buildroot, u-boot).

October 2015 - May 2020


Université Paris Salcay (carried at Télécom ParisTech)

Phd in Computer Science

Supervised by Laurent Pautet and Etienne Borde.

October 2015 - January 2020

Université Pierre et Marie Curie (Paris 6)

MSc in Distributed Systems and Applications
September 2013 - September 2015

Université Claude Bernard (Lyon 1)

BSc in Computer Science and Mathematics
September 2010 - June 2013


Journal Papers

  • Generalized Mixed-Criticality Static Scheduling for Periodic Directed Acyclic Graphs on Multi-Core Processors
    Roberto Medina, Etienne Borde and Laurent Pautet
    IEEE Transactions on Computers, 2020
    [ PDF ] [ BibTex ]

International Conferences

  • Scheduling multi-periodic mixed-criticality DAGs on multi-core architectures
    Roberto Medina, Etienne Borde and Laurent Pautet
    IEEE 39th Real-Time Systems Symposium (RTSS), 2018
    [ PDF ] [ BibTex ] [ slides ]
  • Availability enhancement and analysis for mixed-criticality systems on multi-core
    Roberto Medina, Etienne Borde and Laurent Pautet
    Design, Automation and Test in Europe, Conference Exhibition (DATE), 2018
    [ PDF ] [ BibTex ] [ slides ]
  • Directed Acyclic Graphs Scheduling for Mixed-Criticality Systems
    Roberto Medina, Etienne Borde and Laurent Pautet
    Reliable Software Technologies - Ada Europe, 2017
    [ PDF ] [ BibTex ] [ slides ]

International Conferences: Short Papers

  • Work-in-Progress: System-wide DVFS for real-time systems with probabilistic parameters
    Roberto Medina and Liliana Cucu-Grosjean
    IEEE 40th Real-Time Systems Symposium (RTSS), 2019
    [ PDF ] [ BibTex ]
  • Availability analysis for synchronous data-flow graphs in mixed-criticality systems
    Roberto Medina, Etienne Borde and Laurent Pautet
    IEEE 11th Symposium on Industrial Embedded Systems (SIES), 2016
    [ PDF ] [ BibTex ]


  • Deployment of Mixed-Criticality and Data-driven Systems on Multi-core Architectures
    Roberto Medina
    Ph.D. thesis, Télécom ParisTech, 2019
    [ PDF ] [ BibTex ]
  • Conception & Development of Safety-Critical Systems for Multi-core Architectures
    Roberto Medina
    M.Sc. thesis, Université Pierre et Marie Curie (Paris 6), 2015
    [ PDF ]


Programming Languagess
  • C
  • C++
Operating systems
  • General public Arch Linux, Ubuntu, Debian, ...
  • Embedded Buildroot, U-boot.
  • Real-time Zephyr, OSEK, POK, RTEMS.

  • Model Based Engineering OSATE, Eclipse Modeling Framework.
  • Model Checking UPAAL, PRISM, CozyVerif, MiniZinc.
  • Real-time Zephyr, OSEK, POK, RTEMS.


  • Track/Fixed geared bikes
  • Music (bass guitar)